The present invention relates to a method and apparatus for detecting patterns and defects therein as in circuit patterns formed on an LSI, TFT (Thin Film Transistor), or the like as objects of inspection. The defects may, for example, be defects in shape, foreign matter, discolorations defects or the like.
Integrated circuits such as LSI are tending to increase in packaging density and are provided with more miniaturized components. In fabricating such miniaturized circuit patterns, detection of defects in the patterns has great importance in evaluation of the quality of the products. It is already difficult to detect defects by visual inspection and to use a large amount of manpower for detecting the defects by visual inspection is not sufficient and, hence, there is increasing demand for automated defect detection.
A method and apparatus for converting image information of the surface of a semiconductor device obtained by an optical microscope or electronic microscope into an electric signal using a camera tube or image pickup device and subjecting the signal to certain signal processing to thereby detect defects in the semiconductor device is known as described, for example, in Semiconductor World (June, 1984) pp. 112 to 119, or Japanese Laid-open Patent Publication No. 59-192943. Such an apparatus is illustrated in FIG. 14, wherein a circuit pattern on a wafer 1 illuminated by a lamp 2 is enlarged and detected by an objective lens 3 and an image sensor 4. The thus detected gray image of the circuit pattern is compared in a defect detection device 6 with the image of a chip 7a (adjoining chip) detected and stored in an image memory 5 one step before and, thereby, the presence of a defect is determined. The detected image is simultaneously stored in the image memory 5 (turned into a stored image) and used for inspection by comparison for the next chip 7b. A block diagram arrangement of the defect detection device 6 for determination of existence of a defect is shown in FIG. 15. The detected image and the stored image are aligned with each other in an alignment circuit 6a and a difference image between the aligned detected image and stored image is obtained by a difference image detector circuit 6b. This signal is binarized by a binarization circuit 6c for detecting a defect. Thus, a defect 8a is detected with the described arrangement.
More minutely arranged LSI's are being fabricated and there are also appearing submicron LSI's such that it is becoming more difficult for the above-described apparatus to detect minute defects. If the miniaturization of components and multilayer structure of circuit patterns on LSI's are developed still more in the future, it is assumed that detection of defects on the order of 0.1 to 0.3 .mu.m in such complicated and miniaturized multilayer patterns will become necessary, and such detection cannot be reliably performed with use of only the aforementioned apparatus.
A method for comparison of patterns is also disclosed in a paper entitled, "Computer Controlled Imaging System for Automatic Hybrid Inspection" (Solid State Technology/October 1980). According to the method described therein, every time a pattern is detected, the detected pattern is temporarily stored and simultaneously compared with a pattern that was detected and stored immediately before, whereby detection of a defect in the pattern is achieved. More specifically, the patterns as the object of pattern detection may be patterns on semiconductor wafers for memory LSI's, patterns for TFT, patterns on printed-wiring boards, patterns on ceramic boards, and patterns of masks and reticles used in the processes fabricating the above mentioned devices. Hereinafter, description will be made about patterns on semiconductor wafers as an example, but the same description will equally be applicable to other patterns.
The patterns as the units of chips on a semiconductor wafer are finally separated into individual chips. Before being separated, a large number of chips as individual products are mounted on one slice of the wafer. The patterns of the chips are all made alike, but each pattern as a unit of a chip is formed of a pattern portion in which memory cells or the like formed in identical patterns are periodically arranged at regular intervals and a pattern portion in which peripheral circuits or the like are arranged less periodically.
Now, the principle of a method conventionally practiced for detecting defects in patterns will be further described with reference to FIG. 35, taking a pattern on a chip, as an example, and which corresponds to the patterns illustrated in FIG. 15. In this method, in view of the fact that all chips have the same patterns and, within each chip, patterns corresponding to its cells are periodically arranged at regular intervals, when a pattern on one chip is detected, the pattern is stored, and then, when a pattern on another chip, which should be equal to the previously detected pattern, is detected, the pattern is compared with the stored pattern, and thereby, a defect is detected. FIGS. 35(a), (b), and (c) respectively show a stored pattern, a detected pattern, and a difference between the patterns (difference obtained as the result of the comparison), and it is arranged such that there occurs virtually no difference between patterns when there is no defect in either of the stored pattern and the detected pattern. However, when there is a defect present in either of the patterns, a difference between patterns is produced at the position where the defect is present. Thus, it is arranged such that a pattern defect is detected by detecting the portion where such a difference between patterns is produced. At that time, if there is produced a pattern difference, it can be determined that a defect is present in either of the patterns, but it cannot be determined in which of the patterns the defect is present. In practice, however, there are various ways to determine that, but the explanation thereof is omitted herein.
The pattern on one chip was compared with that on another chip in the foregoing method (which method will hereinafter be called the "two-chip comparison method"). It can also be arranged such that pattern comparison is carried out for cell patterns within the same chip (which method will hereinafter be called the "two-cell comparison method"). The above described method of comparison is not only applicable to patterns on a wafer, but is also applicable with relative ease to a general pattern to be defined as a superordinate concept of the pattern, although there is no such concept as chips or cells involved therein, such as members having the same patterns or a member in which the same patterns are periodically arranged at regular intervals.
Generally, in the two-cell comparison method, the error level detected in a normal portion is lower than that in the two-chip comparison method and, hence, the discrimination between a defective pattern portion and a normal pattern portion in the two-cell comparison method is easier. FIG. 36(a) shows a detected signal waveform of a pattern obtained along a pattern detecting line, FIG. 36(b) and FIG. 36(c) respectively show a waveform for the two-cell comparison and a waveform for the two-chip comparison to be compared with the detected waveform, FIG. 36(d) and FIG. 36(e) respectively show a waveform obtained two-chip comparison method. As apparent from these waveforms, the signal level of the difference signal a the portion of the normal pattern is relatively low in the two-cell comparison method, while that in the two-chip comparison method is high. This is because, in the two-cell comparison method, the patterns are compared within the same chip and, in addition, one pattern is compared with another pattern located quite close to it and, hence, the factors which produce errors in the normal pattern portion are not so great. As a result, the difference waveform at the normal pattern portion detected in the two-cell comparison method is at a relatively lower signal level while that detected in the two-chip comparison method is at a relatively higher level. Meanwhile, the signal levels of the difference signals at the portion including a defect obtained by the two-cell comparison method and by the two-chip comparison method are considered virtually of the same level. Accordingly, when discriminating a portion with a normal pattern from a portion with a defective pattern by binarizing the signal levels of the difference signals, the threshold value tolerance used for the discrimination can be made larger in the two-cell comparison method than in the two-chip comparison method and, therefore, the discrimination between the portion with a defective pattern and the portion with a normal pattern becomes easier in the two-cell comparison method than in the two-chip comparison method.
Conventionally, in detecting a defect in a pattern on a wafer, for example, the defect detection is performed either by only applying the two-chip comparison method over the entire surface of the wafer or by specifying the coordinate for the two-cell comparison and applying the two-cell comparison method to the portion where two-cell comparison is applicable and the two-chip comparison method to the portion where two-cell comparison method is not applicable. Here, the portion where the two-cell comparison is applicable is such a portion within a chip defined as the portion of a pattern where memory cells are periodically arranged at intervals of a predetermined pitch, and the portion where the two-cell comparison is not applicable is such a portion defined as the portion of a pattern within a chip other than the portion where two-cell comparison is applicable, or, more particularly, as the portion where patterns are arranged less periodically, such as a portion where peripheral circuits are formed and, hence, detection of a defect in the patterns is possible only by the two-chip comparison method.
Pattern defect detection has conventionally been performed as described above, but whichever method has been used, there has been some problem or inconvenience particularly related to each respective method. That is, when the two-chip comparison method is used, since a pattern defect is detected by the two-chip comparison method even at the portion where two-cell comparison is applicable, the threshold value tolerance inevitably becomes small. On the other hand, when the two-cell comparison method is used, preprocessing is required so as to set up in advance the coordinate of the portion where the two-cell comparison is applicable, which differs with the different types of wafers.
Another prior art pattern recognition arrangement is described in Japanese Laid-Open Patent Publication No. 57-196377, includes means for detecting a pattern, means for storing the detected pattern, means for pixel-wise alignment of the pattern detected and stored one step before with the pattern currently detected, and means for extracting and evaluating the error between the aligned two patterns, whereby it is adapted such that a defect in the pattern is recognized through the comparison. The objects of pattern recognition include a pattern on a memory LSI as shown in FIG. 38, a pattern of TFT, a pattern on a printed-wiring board, a pattern on a ceramic board, and patterns of masks and reticles used in the fabricating processes of the above mentioned devices. In view of the fact that all the chips have completely the same patterns, first, a pattern is detected and stored, and then another pattern, which should be the same as the previous one, is detected, the stored pattern is brought into pixel-wise alignment with the detected image (which pixel-wise alignment is a state where, having differences between the detected pattern and the stored pattern summed up for pixels all over the area of the image and the summation performed with the stored pattern shifted one pixel at a time relative to the detected pattern, the images are brought into a position where the sum total of the differences becomes a minimum, i.e., the two images are best aligned), and the errors between the two patterns in alignment are extracted and evaluated. When there is no defect in either pattern, the difference between the patterns is small, but when there is a defect in either of the patterns, a considerable difference is produced between the patterns at the defective portion. Therefore, by comparing the patterns and detecting the position where an error is produced, a pattern defect can be recognized. At that time, if a difference is detected through the comparison, it can be said that there is a defect in either of the patterns, but it is not possible to determine in which pattern the defect is present.
A normal pattern on a wafer as the object of inspection exhibits different patterns from location to location due to various error causing factors. Therefore, a difference between patterns can not always be determined to be a defect, and it becomes difficult to discriminate a small defect from an error in the normal portion. The distinction between a defect and an error in the normal portion will first be defined. An error in the normal portion is defined to be such that the same pattern in the vicinity of the portion in question has also a similar error. On the other hand, a defect is defined to be a localized difference and such that the same pattern in the vicinity has no similar error. It is further assumed that an allowable dimensional error in the normal portion is larger than the minimum defect size to be recognized. Of course there are some exceptions, but such exceptions are not considered herein.
Utilizing the above definitions, a method in which a difference between patterns is determined to be a defect will encounter a problem as shown in FIG. 39. All patterns in FIG. 39 are shown in binary images for simplicity of explanation. FIG. 39(a) shows a case where a stored pattern and a detected pattern are compared in a normal portion having an allowable dimensional error, FIG. 39(b) shows a case where a stored normal pattern and a detected defective pattern are compared for patterns involving a defect of the least size to be recognized, and FIG. 39(c) and FIG. 39(d) respectively show the difference between the patterns in FIG. 39(a) and that in FIG. 39(b). Comparing FIG. 39(c) with FIG. 39(d), the area of the difference between the patterns in the normal portion is larger than the area of the difference between the patterns in the defective portion, and this makes the detection of a defect difficult. As such, a method must be devised to easily perform discrimination between the normal pattern with an error and a defect and to recognize features of patterns such as a discrepancy between patterns or deformation of a pattern can be easily performed.